Kontroler Ethernet 100BaseTX, 10BaseT BIU LQFP
- Nr art. RS:
- 177-3534
- Nr części producenta:
- KSZ8851-16MLLI
- Producent:
- Microchip
Zapas chwilowo wyczerpany, wysyłka nastąpi, gdy produkt będzie znowu dostępny
Dodano do koszyka
Cena netto szt. (na tacce 250)
22,81 zł
(bez VAT)
28,06 zł
(z VAT)
| Produkty | Per unit | Per Tray* |
| 250 + | 22,81 zł | 5 702,75 zł |
| *cena za opakowanie | ||
- Nr art. RS:
- 177-3534
- Nr części producenta:
- KSZ8851-16MLLI
- Producent:
- Microchip
Dane techniczne
Atesty i certyfikaty
- Kraj pochodzenia:
- US
Szczegółowe dane produktu
The KSZ8851 is a single-port controller chip with a SPI or 8-/16-/32-bit non-PCI CPU interface. Available in 32-/48-/128-pin packages, the KSZ8851 is for applications requiring cost-effective, high-throughput Ethernet connectivity in traditional embedded systems with MCUs or MPUs.
Integrated MAC and PHY Ethernet Controller
Designed for high performance and high throughput applications
Supports 10BASE-T/100BASE-TX
Supports full-duplex flow control and half-duplex back pressure collision flow control
Supports DMA-slave burst data read and write transfers
Supports IP Header (IPv4)/TCP/UDP/ICMP checksum generation and checking
Supports IPv6 TCP/UDP/ICMP checksum generation and checking
Automatic 32-bit CRC generation and checking
Simple SRAM-like host interface easily connects to most common embedded MCUs.
Supports multiple data frames for transmit and receive without address bus and byte-enable signals
Supports both Big- and Little-Endian processors
Designed for high performance and high throughput applications
Supports 10BASE-T/100BASE-TX
Supports full-duplex flow control and half-duplex back pressure collision flow control
Supports DMA-slave burst data read and write transfers
Supports IP Header (IPv4)/TCP/UDP/ICMP checksum generation and checking
Supports IPv6 TCP/UDP/ICMP checksum generation and checking
Automatic 32-bit CRC generation and checking
Simple SRAM-like host interface easily connects to most common embedded MCUs.
Supports multiple data frames for transmit and receive without address bus and byte-enable signals
Supports both Big- and Little-Endian processors
.
Dane techniczne
Atrybut | Parametr |
|---|---|
| Typ sieci fizycznej | 100BaseTX, 10BaseT |
| Interfejs hosta | BIU |
| Interfejs sieciowy | 100BaseTX, 10BaseT |
| Interfejs | Sterownik IC |
| Tryb komunikacji | Pełny dupleks, półdupleks |
| Szybkość transmisji danych | 100Mbps |
| Tryb pętli zwrotnej | Wewnętrzny |
| Obsługiwany standard | IEEE 802.3u, IEEE 802.3x |
| Typ montażu | Montaż powierzchniowy |
| Typ opakowania | LQFP |
| Liczba styków | 48 |
| Automatyczne negocjowanie | Tak |
| Obsługa DMA | Tak |
| Typowe robocze napięcie zasilania | 3,3 V |
| Wymiary | 7.1 x 7.1 x 1.45mm |
| Minimalna temperatura robocza | -40°C |
| Maksymalna temperatura robocza | +85°C |